Xilinx Design Summary

PICOBLAZE_STARTER1 Project Status
Project File:	Picoblaze_Starter1.ise	Current State:	Programming File Generated
Module Name:	PicoBlaze_System2	Errors:	No Errors
Target Device:	xc3s500e-4fg320	Warnings:	3 Warnings
Product Version:	ISE 9.2.04i	Updated:	ma 16. mar 13:49:38 2009

PICOBLAZE_STARTER1 Partition Summary
No partition information was found.

Device Utilization Summary
Logic Utilization	Used	Available	Utilization	Note(s)
Number of Slice Flip Flops	171	9,312	1%
Number of 4 input LUTs	267	9,312	2%
Logic Distribution
Number of occupied Slices	212	4,656	4%
Number of Slices containing only related logic	212	212	100%
Number of Slices containing unrelated logic	0	212	0%
Total Number of 4 input LUTs	380	9,312	4%
Number used as logic	267
Number used as a route-thru	37
Number used for Dual Port RAMs	16
Number used for 32x1 RAMs	52
Number used as Shift registers	8
Number of bonded IOBs	33	232	14%
IOB Flip Flops	5
Number of Block RAMs	1	20	5%
Number of GCLKs	2	24	8%
Number of BSCANs	1	1	100%
Number of MULT18X18SIOs	1	20	5%
Total equivalent gate count for design	77,434
Additional JTAG gate count for IOBs	1,584

Performance Summary
Final Timing Score:	0	Pinout Data:	Pinout Report
Routing Results:	All Signals Completely Routed	Clock Data:	Clock Report
Timing Constraints:	All Constraints Met