| LEKTION2_VHDL1 Project Status | |||
| Project File: | Lektion2_VHDL1.ise | Current State: | Programming File Generated |
| Module Name: | test1_af_muxdisp |
|
No Errors |
| Target Device: | xc3s100e-4tq144 |
|
18 Warnings |
| Product Version: | ISE 9.2.02i |
|
fr 7. sep 10:50:20 2007 |
| LEKTION2_VHDL1 Partition Summary | |||
| No partition information was found. |
| Device Utilization Summary | ||||
| Logic Utilization | Used | Available | Utilization | Note(s) |
| Number of Slice Flip Flops | 42 | 1,920 | 2% | |
| Number of 4 input LUTs | 101 | 1,920 | 5% | |
| Logic Distribution | ||||
| Number of occupied Slices | 66 | 960 | 6% | |
| Number of Slices containing only related logic | 66 | 66 | 100% | |
| Number of Slices containing unrelated logic | 0 | 66 | 0% | |
| Total Number of 4 input LUTs | 101 | 1,920 | 5% | |
| Number of bonded IOBs | 23 | 108 | 21% | |
| Number of GCLKs | 2 | 24 | 8% | |
| Number of RPM macros | 44 | |||
| Total equivalent gate count for design | 966 | |||
| Additional JTAG gate count for IOBs | 1,104 | |||
| Performance Summary | |||
| Final Timing Score: | 0 | Pinout Data: | Pinout Report |
| Routing Results: | All Signals Completely Routed | Clock Data: | Clock Report |
| Timing Constraints: | All Constraints Met | ||
| Detailed Reports | |||||
| Report Name | Status | Generated | Errors | Warnings | Infos |
| Synthesis Report | Current | fr 7. sep 09:54:00 2007 | 0 | 13 Warnings | 2 Infos |
| Translation Report | Current | fr 7. sep 09:54:07 2007 | 0 | 0 | 0 |
| Map Report | Current | fr 7. sep 09:54:12 2007 | 0 | 3 Warnings | 3 Infos |
| Place and Route Report | Current | fr 7. sep 09:54:22 2007 | 0 | 1 Warning | 2 Infos |
| Static Timing Report | Current | fr 7. sep 09:54:25 2007 | 0 | 0 | 3 Infos |
| Bitgen Report | Current | fr 7. sep 10:14:28 2007 | 0 | 1 Warning | 0 |